Ziatech Corporation ZT 89CT04 manuels

Manuels d'utilisation et guides de l'utilisateur pour PC/postes de travail Ziatech Corporation ZT 89CT04.
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Table des matières

ZT 8808A/8809A

1

V20 Single Board Computers

1

ZIATECHWARRANTY

2

CONTENTS

7

Contents

10

ILLUSTRATIONS

16

Illustrations

17

INTRODUCTION

18

FEATURES OF THE ZT 8809A

21

Introduction

22

FUNCTIONAL BLOCKS

23

GETTING STARTED

31

UNPACKING

32

WHAT’S IN THE BOX?

33

SYSTEM REQUIREMENTS

34

INSTALLING THE ZT 8809A

37

Getting Started

38

128K EPROM

44

256K EPROM

44

128K RAM

44

ZT E:> or ZT P:>

47

I/O ADDRESSING

52

THEORY OF OPERATION

56

STD BUS COMPATIBILITY

59

MEMORY AND I/O

59

SERIAL COMMUNICATIONS

59

INTERRUPTS

63

DIRECT MEMORY ACCESS (DMA)

70

Theory of Operation

72

POWER-FAIL PROTECTION

73

ZT 90020 WALL TRANSFORMER

74

Sense of 4.8 V, R2

77

STATUS INDICATOR (LED)

80

APPLICATION EXAMPLES

85

of ISR to lower word

88

Application Examples

101

Program Code

101

MEMORY AND I/O CAPABILITY

126

MEMORY ADDRESSING

127

MEMORY MAPS

129

Memory and I/O Capability

130

BATTERY BACKUP

135

MEMORY DEVICE LOCATIONS

136

Socket 7D1 Socket 9D1

138

2 00000-7FFFF (512K) Disabled

138

3 Disabled Disabled

138

DEVICE ACCESS TIMES

139

INPUT/OUTPUT ADDRESSING

140

CPU DESCRIPTION (V20)

142

V20 OVERVIEW

143

of each variable

146

used to

147

from the Program Segment

147

RESERVED

149

CPU Description

154

Figure 6–2. V20 Modes

154

(PC) of the

156

DMA SUPPORT

159

RESET STATE

161

WAIT-STATE GENERATOR

162

NUMERIC DATA PROCESSOR (8087)

163

INSTALLING THE zSBC 337

166

COPROCESSOR INTERFACE

169

INTERRUPT/NUMERIC ERRORS

171

REFERENCES

175

Chapter 8

176

Contents Page

176

OVERVIEW

177

ZT 8809A REV A

182

SERIAL REGISTERS

191

Table 8-2

192

Table 8-3

193

CENTRONICS PRINTER INTERFACE

210

USING THE PRINTER PORT

213

REGISTER REGISTER BITS

214

P:\SETUP <CR>

221

OPTIONAL PRINTER CABLE PINOUT

223

PRINTER PORT RESET STATE

224

REAL-TIME CLOCK (DS 1215)

225

OPERATION

227

Real-Time Clock (DS 1215)

229

COUNTER/TIMERS (8254)

233

INTERNAL BUS

235

COUNTER/TIMER ARCHITECTURE

236

D7 D6 D5 D4 D3 D2 D1 D0

239

SC1 SC0 RW1 RW0 M2 M1 M0 BCD

239

Counter/Timers (8254)

247

Table 11-1

247

Read-Back Command Example

247

INTERRUPT CONTROLLER (8259A)

258

I/O PORT ADDRESSES

260

OPERATION OVERVIEW

261

FUNCTIONAL DESCRIPTION

264

PROGRAMMABLE REGISTERS

268

Interrupt Controller (8259A)

270

8259A I/O PORT ADDRESSES

278

EOI COMMANDS

288

FUNCTIONAL DIFFERENCES

293

JUMPER CONFIGURATIONS

301

Jumper Configurations

302

JUMPER DESCRIPTIONS

303

W10A W10B Function

308

W11A W11B Function

309

W12 Function

310

W13A W13B Function

313

W14 Function

314

RS-422/485

314

W38A W38B Function

328

W39 Function

329

W40-W43 Function

330

128 Kbyte EPROM drive

330

64 Kbyte EPROM drive

330

W47A W47B W48 Function

335

W50A W50B Function

336

W51 W52 Function

338

W53 Function

339

DCPWRDWN* on STD bus

339

W54 Function

340

Table A-2

342

Memory Addressing, W55-W59

342

W62 Function

347

W63 Function

348

W64A W64B Function

349

W65A W65B Function

350

W66 Function

351

W68A W68B Function

353

SPECIFICATIONS

357

ELECTRICAL AND ENVIRONMENTAL

358

Specifications

360

Table B-1

360

Table B-2

361

MECHANICAL

362

COMPONENT SIDE

363

CONNECTORS

365

STD 32 STD 32

367

CUSTOMER SUPPORT

386

TROUBLESHOOTING

387

ZT E:> or ZT P:> prompt

390

RELIABILITY

394

WARRANTY

395

TECHNICAL ASSISTANCE

396

RETURNING FOR SERVICE

397

Table des matières

I/O Control Processor

1

ZIATECH 5+5 WARRANTY

2

1998 Ziatech Corporation

3

CONTENTS

9

Contents

10

ILLUSTRATIONS

20

Illustrations

21

INTRODUCTION

23

Introduction

27

FUNCTIONAL BLOCKS

28

GETTING STARTED

33

UNPACKING

34

WHAT’S IN THE BOX?

34

SYSTEM REQUIREMENTS

35

ZT 8832 ICP

36

III. USER’S REFERENCE

47

THEORY OF OPERATION

48

COMMONLY ASKED QUESTIONS

50

DUAL PORT MEMORY

55

BOARD SELECT OPTION

62

STD BUS INTERRUPTS

64

APPLICATION EXAMPLES

71

EXAMPLE 1: V40 INITIALIZATION

72

EXAMPLE 3: WATCHDOG TIMER

88

LP3: LOOP LP3

93

JMP LP2 ; REPEAT

93

CODE ENDS

93

END MAIN

93

PROCESSOR DESCRIPTION (V40)

94

for the string source is the

102

is specified in IY [DI]

102

address

103

The offset

103

the top of

105

MEMORY AND I/O ADDRESSING

117

INTERRUPTS

120

value in the format

122

PFP (IP)

122

8080 EMULATION

127

PROCESSOR CONFIGURATION (V40)

130

Register:WCY2

136

Address:FFF6h

136

76543210

136

Register:RFC

139

Address:FFF2h

139

COUNTER/TIMERS (V40)

142

OVERVIEW

143

ZT 8832 SPECIFICS

144

FUNCTIONAL DESCRIPTION

145

PROGRAMMABLE REGISTERS

148

Note: x = Don’t Care

150

000000SC

151

OPERATION

155

Count value

157

Counter/Timers

160

Figure 7–8. Mode 1 Operation

160

Figure 7–9. Mode 2 Operation

162

INTERRUPT CONTROLLER (V40)

170

———V7 V6 V5 V4 V3

179

00000000

179

M7 M6 M5 M4 M3 M2 M1 M0

181

IL2 IL1 IL0

182

00RP SIL FI

182

SNM EXCN

184

PL2 PL1 PL0

187

Interrupt Controller (V40)

192

DMA CONTROLLER (V40)

201

C0C1C2C3C4C5C6C7

210

C8C9C10C11C12C13C14C15

210

A0A1A2A3A4A5A6A7

211

A8A9A10A11A12A13A14A15

211

A16A17A18A19————

211

SERIAL COMMUNICATIONS (V40)

219

SERIAL COMMUNICATIONS (82050)

235

Serial Communications (82050)

243

Table 11-5

259

ACC Register Summary

259

PARALLEL I/O

261

WATCHDOG TIMER

268

SBX EXPANSION MODULE

276

INSTALLATION

280

NUMERIC DATA PROCESSOR (8087)

281

IV. APPENDICES

288

JUMPER CONFIGURATIONS

289

JUMPER OPTIONS

290

Jumper Configurations

297

Table A-2

297

W44 W45 W46 Interrupt Signal

301

Figure A–2. Jumper Locations

303

CUTTABLE TRACES

304

SPECIFICATIONS

311

ELECTRICAL AND ENVIRONMENTAL

312

Specifications

314

Table B-1

314

Table B-2

315

MECHANICAL

316

COMPONENT SIDE

317

STD 32 STD 32

318

Table B-3

321

J1 Parallel Port Pinout

321

Table B-7

325

1.25"

330

+5 VOLTS

335

CUSTOMER SUPPORT

336

REVISION HISTORY

337

TECHNICAL ASSISTANCE

339

RELIABILITY

340

RETURNING FOR SERVICE

341

GLOSSARY

344

Glossary

348

Table des matières

ZT 89CT04

1

CONTENTS

2

Contents

3

MANUAL ORGANIZATION

6

1. INTRODUCTION

8

FEATURES

10

DEVELOPMENT CONSIDERATIONS

11

FUNCTIONAL BLOCKS

11

Bus Interface

12

2. GETTING STARTED

17

I/O CONFIGURATION

19

CONNECTOR CONFIGURATION

20

JUMPER DESCRIPTIONS

21

3. STD BUS INTERFACE

23

STD 32 BUS COMPATIBILITY

24

STD BUS INTERRUPTS

24

Embedded

28

Computer

28

4. INTERRUPT CONTROLLER

31

Interrupt Architecture

33

Initialization Register ICW1

34

Initialization Register ICW2

35

Initialization Register ICW4

35

Operational Register OCW1

36

Operational Register OCW2

36

Operational Register OCW3

37

Status Register IRR

37

Status Register ISR

37

5. COUNTER/TIMERS

39

Counter/Timer Operating Modes

40

Status Register

42

General Control Register

43

Count Latch Control Register

43

6. DMA CONTROLLER

45

DMA IMPLEMENTATION

47

DMA CONTROLLER OPERATION

48

PINCFG Register

52

DMACFG Register

53

6. DMA Controller

54

Channel 0 Byte Count Bits 0-7

59

Channel 1 Byte Count Bits 0-7

61

DMA Status Register

62

DMA Command Register 1

63

DMA Command Register 2

63

DMA Mode Register 1

64

DMA Mode Register 2

65

DMA Software Request Register

65

DMA Group Channel Mask

66

DMA Bus Size Register

67

DMA Chaining Register

67

DMA Interrupt Enable Register

68

DMA Interrupt Status Register

68

DMA Overflow Enable Register

69

7. REAL-TIME CLOCK

70

Rate Selection

72

Access: Read and Write

73

Access: Read

73

Access: Read

74

8. SERIAL CONTROLLER

75

COM1 RS-485 Architecture

77

COM2 RS-485 Architecture

77

Baud Rate Divisors

79

Divisor Latch LSB

79

Divisor Latch MSB

80

Interrupt Control Register

80

Interrupt Status Register

81

Line Control Register

82

Line Status Register

83

Modem Control Register

83

10. PARALLEL I/O

87

Port Data Register

91

Write Inhibit Register

91

Port Event Sense Register

92

Event Sense Manage Register

93

Bank Address Register

93

Debounce Configure Register

94

Debounce Duration Register

94

Debounce Clock Register

94

Mask Register

95

11. SYSTEM REGISTERS

96

System Register 1

97

12. WATCHDOG TIMER

99

PROGRAMMABLE REGISTERS

100

Watchdog Timer Clear Register

101

ADDITIONAL INFORMATION

103

13. LOCAL BUS VIDEO

104

14. NUMERIC DATA PROCESSOR

105

15. PROGRAMMABLE LED

106

16. AC POWER FAIL

108

A. JUMPER CONFIGURATIONS

109

Customer Jumper Configuration

110

B. SPECIFICATIONS

116

B. Specifications

118

COMPONENT SIDE

120

Connector Locations

121

P/E Connector Pinout

122

J1 Peripheral Pinout

123

J3 AC Power Fail Pinout

126

J4 Parallel I/O Pinout

127

J5 Memory Expansion Pinout

128

J6 Local Bus Pinout

129

J7 Auxiliary Power Pinout

131

J8 Optional IDE Pinout

132

ZT 90072 Digital I/O Cable

133

ZT 90168 Multiple zVID2 Cable

137

PREVENTING SYSTEM LATCHUP

139

PROTECTING CMOS INPUTS

143

HCPL-2630

144

D. CUSTOMER SUPPORT

146

ZIATECH WARRANTY

147

TRADEMARKS

148


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